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Research and Validation of Flash Extractor's Read Retry Function (Micron)

  • Micron V1 (referred to as Micron in FE, but for ease of version distinction, I'll call it MicronV1) is implemented as a library. Due to the low error rate in early Micron/Intel MLC chips, there was generally no need for error correction through read retries. Therefore, the read retry function was designed to be relatively simple. Based on testing, MicronV1 is suitable for L74 (25nm) process and earlier MLC chips, specifically excluding early MLC chips like 45nm and 60nm



  • Micron V2 is the most commonly used Read Retry (RR) function. It implements the standard Read Retry at address 89h and additionally introduces the Automatic Read Calibration (ARC) feature. It has a wide range of applicability, supporting MLC chips from L84 and L85 processes (20nm) up to the latest QLC chips. However, it appears that Flash Extractor has some issues in implementing this functionality correctly.
  •   About Micron v2 RR ( seems they have become aware of this issue.



  • When the second byte value is 03, errors occur because the ARC function values are limited to 00b, 01b, 10b, and 11b. When input values exceed this range, unpredictable errors may occur. Through testing, it has been observed that when the second byte value is 03, it can lead to a corrupt dump.
  • Due to the aforementioned error, another issue may arise. Before setting another ARC value, it is necessary to send a reset command to the chip to clear the current ARC parameters. However, Flash Extractor uses the traditional reset command FFh (Reset), while according to the specification, sending FDh (Hard Reset) to the chip is the correct approach. Please refer to the Micron specification document for more details:   



  • When using Micron V2 RR alone, there is no issue. The principle is that if an incorrect ARC value of 03 is set, as long as it is not used, when Micron V2 is rerun, the new value will be reset to 00 (ARC disabled state).
  • When used together with Micron V3 and Micron V4, an issue arises if the ARC value is set to 03. This problem occurs because when running V3 and V4, there is no ARC value setting, and no FDh (Hard Reset) is performed. As a result, this error will persist until the chip's power is cycled.



  • Micron V3 is designed for Read Offset Operations, specifically applicable to analog 4-bit/cell chips simulated as 3-bit/cell chips. Currently, Micron V3 is implemented for 4bpc WL mode, which converts QLC to TLC mode through instructions. Micron V3 only supports voltage offset simulation in TLC mode.


  • Indeed, the latest generation QLC chips in the market allow running in SLC/TLC/QLC modes through special instructions. This mode is also supported by Bics4 QLC, Bics5 QLC, Hy3Dv6, and Hy3Dv7.


  • I agree that it might be beneficial to introduce a new voltage offset mode for native 3-bit/cell Micron chips. Following the naming convention, we can call it Micron V3.5, and the only necessary change would be to update the address range from A5-AB to D0-D6.



  • Micron V4, similar to V3, is designed for reading cell internal voltage threshold offset mode, but it is specifically applicable to QLC chips only. Currently, due to the limitation of the reading device not supporting nvddr3 mode (which requires DQS signal) and 6-byte addressing mode, Micron V4 can only be used for the first-generation Micron QLC with the code name N18.


  • At present, Micron V4 comprises 7 register addresses. In the future, if support for more QLC chips is required, additional register addresses will need to be added. For instance, N28A would require 15 register addresses. This flexibility allows for accommodating a wider range of QLC chips in the future.